This invention relates generally to bandgap reference circuits and more particularly to bandgap reference circuits adapted for use in charge balance circuits.
As is known in the art, bandgap reference circuits have widespread use in integrated circuits to provide a reference voltage which is substantially invariant with temperature. The original integrated circuit bandgap reference circuit used bipolar transistors. One such circuit is described in "A Simple Three-Terminal IC Bandgap Reference", by A. P. Brokow, published in IEEE Journal of Solid-State Circuits, vol. SC-9, pp. 388-393, December 1974.
More recently, CMOS technology has been in use for digital circuits and such CMOS circuits frequently require a CMOS bandgap reference circuit. One example of such a circuit is presented in a paper entitled "A Precision CMOS Bandgap Reference", by J. Michejda and S. K. Kim, published in IEEE Journal of Solid-State Circuits, vol. SC-19, no. 6, pp. 1014-1021, December 1984. Such circuit is shown in FIG. 1 and includes a pair of diode-connected bipolar transistors Q1 and Q2, the transistor Q1 having N times the number of emitters of (i.e., N times the emitter area of) transistor Q2, where N is an integer greater than 1. It is noted that a diode-connected transistor provides a p-n junction between the emitter and base terminals thereof, with the collector terminal shorted to the base. These transistors Q1 and Q2 are provided by the substrate bipolar transistor (in this case, p-n-p) that are a by-product of the CMOS process. They are not generally of the same quality as the transistors available in a true bipolar or biCMOS process. In particular, the current gain, beta, and Early voltage, V.sub.A, are poorer. The basic idea is to produce a base-emitter voltage V.sub.BE and have added to it a multiple G of a voltage .DELTA.V.sub.BE such that the sum, V.sub.BE +G.DELTA.V.sub.BE, is a reference voltage which is substantially invariant with temperature.
More particularly, an operational amplifier A1 is provided with a resistor R.sub.2 connected between the output of amplifier A1 and the inverting (-) input of the amplifier. The inverting input (-) is coupled to ground through a resistor R.sub.1 and the diode-connected transistor Q1. The non-inverting input (+) of amplifier A1 is connected to ground through the diode-connected transistor Q2 and to the output of amplifier A1 through the resistor R3. The feedback arranged amplifier A1 drives the junction between resistors R.sub.1 and R.sub.2 to the same voltage as the voltage at the emitter of transistor Q2. With R.sub.2 =R.sub.3, the current through the diode-connected transistor Q1 will be driven to the same value as the current through the diode-connected transistor Q2. However, because of the larger emitter area of transistor Q1, transistor Q1 will have a smaller V.sub.BE than that of transistor Q2. Thus, .DELTA.V.sub.BE, appears across resistor R.sub.1 and the output voltage V.sub.REF of the amplifier may be expressed as: EQU V.sub.REF =V.sub.BE +(1+R.sub.2 /R.sub.1).DELTA.V.sub.BE =V.sub.BE +G.DELTA.V.sub.BE
where .DELTA.V.sub.BE =V.sub.T ln(N)=(kT/q)ln(N), k is Boltzman's constant, T is temperature in degrees Kelvin and q is the charge of an electron. PA1 .DELTA.V.sub.BE =V.sub.T ln(n).
Typically, at 300.degree. K., V.sub.BE has a value of about 650 mV and a temperature coefficient of -2 mV/.degree. K. V.sub.T has a value of 25.9 mV and a temperature coefficient of +86.2 .mu.pV/.degree. K. For a typical value N of 8, .DELTA.V.sub.BE will therefore have a value of 53.8 mV and a temperature coefficient of +179.2 .mu.V/.degree. C. To balance the large negative temperature coefficient of V.sub.BE, G should be 11.2. That is, R.sub.2 /R.sub.1 =10.2. In such case, V.sub.REF =0.65+{11.2.times.0.0538}=1.25 V.
The main limitation to performance achievable by CMOS bandgap circuits is not the substrate bipolars but the poor offset and low frequency noise (1/f) of the CMOS amplifier, A1. The noise and offset are represented by the voltage source V.sub.OS in FIG. 1. The noise and offset add directly to .DELTA.V.sub.BE and therefore see the same high gain G, here 11.2 to the output V.sub.REF. Thus, the V.sub.REF, including the effect of noise and offset, (i.e., V.sub.OS) may be represented as: EQU V.sub.REF =V.sub.BE +[1+(R.sub.2 /R.sub.1)][.DELTA.V.sub.BE +V.sub.OS ].
Another approach to bandgap reference design is the use of a switched capacitor amplifier as shown in FIG. 2 and discussed in U.S. Pat. No. 5,059,820, issued Oct. 22, 1991, entitled "Switched Capacitor Bandgap Reference Circuit Having Time Multiplexed Bipolar Transistor", inventor A. L. Westwick. Here, the basic idea is that V.sub.BE and .DELTA.V.sub.BE voltages are sampled on capacitors C1 and C2, respectively, and combined in the correct proportion to form a substantially temperature invariant reference voltage V.sub.REF. More particularly, a pair of current sources 12, 14 are connected to inputs of switches S1 and S2 respectively, the outputs of such switches being connected to the emitter of diode-connected transistor Q1. The current produced by current source 12 is I and the current produced by current source 12 is nI, where n is an integer greater than one. Switches S2 and S3 close and switches S1 and S4 open during a first of two phases, (i.e., switches S2 and S3 close during the first phase when pulse P1, shown in FIG. 3, is "high" and switches S1 and S4 open during the first phase when pulse P2 is "low"). Switches S2 and S3 open and switches S1 and S4 close during a second of the two phases, (i.e., switches S2 and S3 open during the second phase when pulse P1, shown in FIG. 3, is "low" and switches S1 and S4 close during the second phase when pulse P2 is "high"). In operation, during the first phase, current nI flows through Q1 and during the second phase current I flows through transistor Q1 producing, during the second phase, a smaller V.sub.BE at the emitter of transistor Q1. The difference in V.sub.BE produced at the emitter of Q1 (i.e., .DELTA.V.sub.BE) is sampled by capacitor C2 and charge corresponding to the sampled difference in V.sub.BE is transferred to capacitor C3 during the second phase. Meanwhile, capacitor C1 samples the V.sub.BE produced at the emitter of transistor Q1 during the first phase and transfers charge corresponding to this sampled V.sub.BE to capacitor C3 during the second phase. It is noted that the capacitor C3 is shunted by switch 16 which closes when pulse P3 goes "high", shown in FIG. 3, and opens when pulse P3 goes "low", such pulse P3 being shown on a common time base with the pulses P1 and P2 in FIG. 3. The expression for the voltage produced at the output of amplifier A1 during the second phase (i.e., when pulse P2 is "high", as shown in FIG. 3) may be expressed as: EQU V.sub.REF =[C1/C3]V.sub.BE +[C2/C3].DELTA.V.sub.BE
which may alternatively be expressed as: EQU V.sub.REF =[C1/C3][V.sub.BE +(C2/C1).DELTA.V.sub.BE ],
where now
It is noted that the ratio of C2/C1 is similar in function to the scale factor G described above in connection with FIG. 1. Thus, the ratio C2/C1 is selected so that V.sub.REF is substantially invariant with temperature. Further, the ratio C1/C3 adds additional freedom to enable V.sub.REF to be scaled larger or smaller than the bandgap voltage as required. Furthermore, the .DELTA.V.sub.BE is now set by a current ratio, n, rather than by an emitter ratio, N.
If the amplifier A1, in FIG. 2, has an offset V.sub.OS, then it is possible to show that the second phase voltage is EQU V.sub.REF =V.sub.OS +[C1/C3][V.sub.BE +(C2/C1).DELTA.V.sub.BE ].
The offset voltage receives much less gain than in the previous linear bandgap reference voltage circuit described above in FIG. 1. It is to be noted, however, that the charge injection at the falling edge of pulse P3 will still add an error to V.sub.REF.
One application of a bandgap reference circuit is in a charge balance circuit. One such charge balance circuit is a sigma-delta modulator, such as that shown in FIG. 4. The sigma-delta modulator includes an integrating amplifier (which is comprised of operational amplifier A1 and the integrating capacitors C1) and a pair of summing nodes SN and SP, fed by: (1) an input sampling and charge transfer circuit and, (2) a reference sampling and charge transfer circuit. The output of the operational amplifier A1 is fed to a comparator (via an optional filter, not shown). The comparator is sampled on the rising edge of clock signal, EN, by a D-type flip/flop to produce true and complementary outputs, Y, YB. A controller produces the clock signals EN, P1 and P2. During phase 2 both the upper and lower CREF capacitors produce a charge sample for transfer. These charge samples are of opposite sign, i.e., the charge sample transferred from the upper CREF capacitor causes current to flow from right to left through the summing node to which it is connected while the charge sample transferred from the lower CREF capacitor causes current to flow from left to right through the summing node to which it is connected. The modulator output directs these charge samples to the appropriate summing node to maintain the integrator outputs bounded and thereby balance the charge produced by the reference sampling and charge transfer circuit with the charge produced by the input sampling and charge transfer circuit. Thus, the output Y is a train of pulses, such train having an average value over time proportional to the input signal. Such charge balance circuit may be used as an analog to digital converter to convert the input signal into corresponding digital words as when the train of output pulses is fed by the modulator to a decimation filter, or as a voltage to frequency converter where the train of pulses have a frequency related to the input signal.
More particularly, referring to FIG. 4, a charge balance circuit, here a sigma delta modulator, is shown to include the integrating amplifier which is comprised of operational amplifier A1 and the integrating capacitors C1. The inverting (-) and non-inverting (+) inputs of A1 are connected to nodes SN and SP, respectively. The modulator includes: (1) a reference sampling and charge transfer circuit comprising switches arranged as shown for sampling a reference signal, here bandgap reference voltage, V.sub.REF, and transferring charge samples corresponding to such sampled reference signal to the integrating capacitors, and (2) an input sampling and charge transfer circuit having switches arranged as shown for sampling an input signal and transferring charge samples corresponding to such sampled input signal to the integrating capacitors. The output of the integrating amplifier is fed to the comparator. The output of the comparator is fed to the D-type flip/flop. The output of the D-type flip/flop (i.e., the modulator output) produces the control signal for some of the switches in the reference sampling and charge transfer circuit. The reference signal, as noted above, is a bandgap reference signal, V.sub.REF, produced by one of the bandgap reference voltage circuits described above in connection with FIGS. 1 and 2, for example.
In operation, two input capacitors, C.sub.IN, sample the modulator input voltage, V.sub.IN, during a first phase and forward, (i.e., transfer) corresponding charge samples to the two summing nodes SN and SP and onto the integrating capacitors, C1, during a second phase. Two reference capacitors, C.sub.REF, sample the bandgap reference voltage, V.sub.REF , during the first phase and forward corresponding charge samples to the summing nodes and integrating capacitors, C1, during the second phase. The modulator output signal Y (i.e., the output of the comparator) and its complement YB, determine to which summing node the charge samples from the upper and lower capacitors C.sub.REF are delivered. To put it another way, the modulator output Y controls the polarity of the charge samples transferred to the summing nodes by the reference sampling and charge transfer circuit. For example, if Y=logic 0 (and YB=logic 1), the charge sample from the upper capacitor C.sub.REF is delivered to SN and that from the lower C.sub.REF is delivered to SP. The net result is that V.sub.OUT+ will increase and V.sub.OUT- will decrease by the same amount. Similarly, if Y=logic 1 (and YB=logic 0), the charge sample from the upper capacitor C.sub.REF is delivered to SP and that from the lower C.sub.REF is delivered to SN. The net result is that V.sub.OUT+ decreases and V.sub.OUT- increases.
Here again, the circuit used to produce the bandgap reference voltage when the modulator is produced using CMOS technology suffers from the effects described above in connection with FIGS. 1 and 2.